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DATA SHEET
MOS INTEGRATED CIRCUIT
PD178002, 178003
8-BIT SINGLE-CHIP MICROCONTROLLERS
The PD178002 and 178003 are 8-bit single-chip CMOS microcontrollers that incorporate hardware for digital tuning systems. The CPU uses the 78K/0 architecture, which makes it easy to implement high-speed access to internal memory and control of peripheral hardware. Also, the instructions used are the high-speed 78K/0 instructions, suitable for system control. The peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial interface, power-on-clear circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer, and a frequency counter. The PD178P018A, one-time PROM or EPROM versions that can be operated in the same supply voltage range as for the mask ROM versions, and various development tools, are also available. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
PD178003 Subseries User's Manual:
U13033E
78K/0 Series User's Manual -- Instructions: U12326E
FEATURES
* Program memory (ROM) capacity
PD178002: 16 Kbytes PD178003: 24 Kbytes
* Data memory (RAM) capacity: 512 bytes * Instruction cycle: 0.44 s (4.5 MHz crystal resonator used) * Selected peripheral hardware of the PD178018A Subseries General-purpose I/O ports, A/D converter, serial interface, timer, frequency counter, power-on-clear circuits. * On-chip hardware for a PLL frequency synthesizer. Dual modulus pre-scaler, programmable divider, phase comparator, charge pump. * Vector interrupt sources: 8 * Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation) VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower) VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U12628EJ3V0DS00 (3rd edition) Date Published December 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1997, 1999
PD178002, 178003
APPLICATIONS
Car stereo, home stereo systems.
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch)
PD178002GC-xxx-3B9 PD178003GC-xxx-3B9
Remark xxx indicates ROM code suffix.
PD178003 AND PD178018A SUBSERIES LINEUP
PD178P018A
80 pins
PROM: 60 KB
RAM: 3 KB
80 pins
PD178018A
ROM: 60 KB
RAM: 3 KB
PD178018A Subseries
80 pins
PD178016A
ROM: 48 KB
RAM: 3 KB
80 pins
PD178006A
ROM: 48 KB
RAM: 1 KB
80 pins
PD178004A
ROM: 32 KB
RAM: 1 KB
80 pins
PD178003
ROM: 24 KB
RAM: 0.5 KB
PD178003 Subseries
80 pins
PD178002
ROM: 16 KB
RAM: 0.5 KB
2
Data Sheet U12628EJ3V0DS00
PD178002, 178003
OVERVIEW OF FUNCTIONS
Part Number Item Internal memory ROM (ROM configuration) High-speed RAM 16 Kbytes (mask ROM) 512 bytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) 0.44 s/0.88 s/1.78 s/3.56 s/7.11 s/14.22 s (with 4.5 MHz crystal resonator used) * * * * 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjust, etc. 62 1 54 4 3 24 Kbytes (mask ROM)
PD178002
PD178003
General-purpose registers Minimum instruction execution time Instruction set
I/O port
Total: CMOS input: CMOS I/O: N-ch open-drain I/O: N-ch open-drain output:
A/D converter Serial interface Timer Buzzer (BEEP) output Vectored interrupt sources Test input PLL frequency synthesizer Division mode Maskable Software
8-bit resolution x 3 channels * 3-wire serial I/O mode: 1 channel * Basic timer (timer carry FF (10 Hz)): * 8-bit timer/event counter: 1.5 kHz, 3 kHz, 6 kHz Internal: 5, external: 2 1 Internal: 1 Two types * Direct division mode (VCOL pin) * Pulse swallow mode (VCOH and VCOL pins) 7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz) Error out output: 2 Unlock detectable by program * Frequency measurement * AMIFC pin: for 450 kHz count * FMIFC pin: for 450 kHz/10.7 MHz count * HALT mode * STOP mode * Reset by RESET pin * Reset by power-on clear circuit (3-value detection) * Detection of less than 4.5 VNote (CPU clock: fX) * Detection of less than 3.5 VNote (CPU clock: fX/2 or less and on power application) * Detection of less than 2.5 VNote (in STOP mode) * VDD = 4.5 to 5.5 V (with PLL operating) * VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less) * VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX) * 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) 1 channel 2 channels
Reference frequency Charge pump Phase comparator Frequency counter
Standby function Reset
Supply voltage
Package One-time PROM
PD178P018A
Note
These voltage values are maximum values. The reset is actually executed at a voltage lower than these values.
Data Sheet U12628EJ3V0DS00
3
PD178002, 178003
TABLE OF CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 5 2. BLOCK DIAGRAM .............................................................................................................................. 7 3. PIN FUNCTIONS ................................................................................................................................. 3.1 Port Pins ..................................................................................................................................... 3.2 Non-port Pins ............................................................................................................................. 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ......................................... 8 8 9 10
4. MEMORY SPACE ................................................................................................................................ 13 5. PERIPHERAL HARDWARE FUNCTION FEATURES ........................................................................ 5.1 Ports ............................................................................................................................................ 5.2 Clock Generator ......................................................................................................................... 5.3 Timer ........................................................................................................................................... 5.4 Buzzer Output Control Circuit .................................................................................................. 5.5 A/D Converter ............................................................................................................................. 5.6 Serial Interfaces ......................................................................................................................... 5.7 PLL Frequency Synthesizer ...................................................................................................... 5.8 Frequency Counter .................................................................................................................... 14 14 15 15 17 18 19 20 21
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS .......................................................................... 22 6.1 Interrupt Functions .................................................................................................................... 22 6.2 Test Function ............................................................................................................................. 25 7. STANDBY FUNCTION ........................................................................................................................ 26 8. RESET FUNCTION .............................................................................................................................. 26 9. INSTRUCTION SET ............................................................................................................................. 27 10. ELECTRICAL SPECIFICATIONS ..................................................................................................... 29 11. PACKAGE DRAWINGS .................................................................................................................... 38 12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 39 APPENDIX A. DIFFERENCES AMONG PD178003 AND PD178018A SUBSERIES ........................ 40 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 41 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 44
4
Data Sheet U12628EJ3V0DS00
PD178002, 178003
1. PIN CONFIGURATION (TOP VIEW)
* 80-PIN PLASTIC QFP (14 x 14 mm, 0.65 mm pitch)
PD178002GC-xxx-3B9 PD178003GC-xxx-3B9
P10/ANI0 P11/ANI1 P12/ANI2 P13 P14 P15 P20/SI1 P21/SO1 P22/SCK1 P23 P24 P25 P26 P27 P132 P133 P134 P40 P41 P42
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RESET VDD REGOSC X1 X2 GND REGCPU P06 P05 P04 P03 P02 P01/INTP1 P00/INTP0 P125 P124 P123 P122 P121 P120
P37 P36/BEEP P35 P34/TI2 P33/TI1 P32 P31 P30 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54
Cautions 1. Connect the IC (Internally Connected) pin directly to GND. 2. Connect VDDPORT and VDDPLL pins to VDD. 3. Connect the GNDPORT and GNDPLL pins to GND. 4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1 F capacitor.
GNDPORT VDDPORT P43 P44 P45 P46 P47 AMIFC FMIFC VDDPLL VCOH VCOL GNDPLL EO0 EO1 IC P50 P51 P52 P53
Data Sheet U12628EJ3V0DS00
5
PD178002, 178003
AMIFC: BEEP: EO0, EO1: FMIFC: GND: GNDPLL: GNDPORT: IC: P00 to P06: P10 to P15: P20 to P27: P30 to P37: P40 to P47: P50 to P57: AM Intermediate Frequency Counter Input Buzzer Output Error Out Output FM Intermediate Frequency Counter Input Ground PLL Ground Port Ground Internally Connected Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 P60 to P67: Port 6
ANI0 to ANI2: A/D Converter Input
P120 to P125: Port 12 P132 to P134: Port 13 REGCPU : REGOSC : RESET: SCK1: SI1: SO1: TI1, TI2: VDD: VDDPLL: VDDPORT: X1, X2: Regulator for CPU Power Supply Regulator for Oscillator Reset Input Serial Clock Input/Output Serial Data Input Serial Data Output Timer Clock Input Power Supply PLL Power Supply Port Power Supply Crystal Resonator Connection
INTP0, INTP1: Interrupt Inputs
VCOL, VCOH: Local Oscillator Input
6
Data Sheet U12628EJ3V0DS00
PD178002, 178003
2. BLOCK DIAGRAM
P00 6 6 P01 to P06 P10 to P15
TI1/P33
8-bit timer/ event counter 1 8-bit timer/ event counter 2
Port 0
TI2/P34
Port 1
Basic timer
Port 2
8
P20 to P27
SI1/P20 SO1/P21 SCK1/P22 ANI0/P10 to ANI2/P12 INTP0/P00 INTP1/P01
Port 3 Serial interface 1 Port 4 3 A/D Converter 78K/0 CPU core
8
P30 to P37
8
P40 to P47
ROM
Port 5
8
P50 to P57
Interrupt control Port 6 Buzzer output Port 12 6 P120 to P125 8 P60 to P67
BEEP/P36
RAM
Port 13
3
P132 to P134
RESET X1 X2 VDDPORT GNDPORT VDD
RESET CPU System control Peripheral
Frequency counter
AMIFC FMIFC
PLL
EO0 EO1 VCOL VCOH
REGOSC REGCPU GND
Voltage regulator
VOSC VCPU
PLL voltage regulator
VDDPLL GNDPLL
IC
Remark The internal ROM capacity varies depending on the product.
Data Sheet U12628EJ3V0DS00
7
PD178002, 178003
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name P00 P01 P02 to P06 P10 to P12 P13 to P15 P20 P21 P22 P23 to P27 P30 to P32 P33 P34 P35 P36 P37 P40 to P47 I/O Port 4 8-bit input/output port Input/output mode can be specified in 8-bit units. The test input flag (KRIF) is set to 1 by falling edge detection. Port 5 8-bit input/output port Input/output mode can be specified in 1-bit units. Port 6 8-bit input/output port Input/output mode can be specified in 1-bit units. P120 to P125 P132 to P134 I/O Port 12 6-bit input/output port Input/output mode can be specified in 1-bit units. Port 13 3-bit output port N-ch open-drain output port. Input -- Middle voltage N-ch open-drain input/output port LEDs can be driven directly. Input BEEP -- -- I/O Port 3 8-bit input/output port Input/output mode can be specified in 1-bit units. Input TI1 TI2 -- I/O I/O Port 1 6-bit input/output port Input/output mode can be specified in 1-bit units. Port 2 8-bit input/output port Input/output mode can be specified in 1-bit units. Input SI1 SO1 SCK1 -- -- I/O Input I/O Port 0 7-bit input/output port Function Input only Input/output mode can be specified in 1-bit units. After Reset Input Input Alternate Function INTP0 INTP1 -- Input ANI0 to ANI2 --
P50 to P57
I/O
Input
--
P60 to P63 P64 to P67
I/O
Input
--
Output
--
--
8
Data Sheet U12628EJ3V0DS00
PD178002, 178003
3.2 Non-port Pins
Pin Name INTP0, INTP1 SI1 SO1 SCK1 TI1 TI2 BEEP ANI0 to ANI5 EO0, EO1 VCOL VCOH AMIFC FMIFC RESET X1 X2 REGOSC REGCPU VDD GND VDDPORT GNDPORT VDDPLLNote GNDPLLNote IC Output Input Output Input Input Input Input Input Input -- -- -- -- -- -- -- -- -- -- Oscillation regulator. Connect to GND via a 0.1 F capacitor. CPU power supply regulator. Connect to GND via a 0.1 F capacitor. Positive power supply Ground Positive power supply for port block Ground for port block Positive power supply for PLL Ground for PLL Internally connected. Connect directly to GND or GNDPORT. Input Output I/O Input I/O Input Function External maskable interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. Serial interface serial data input Serial interface serial data output Serial interface serial clock input/output External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2) Buzzer output A/D converter analog input Error out output from charge pump of the PLL frequency synthesizer Inputs PLL local band frequency (In HF, MF mode) Inputs PLL local band frequency (In VHF mode) Inputs AM intermediate frequency counter Inputs FM intermediate frequency or AM intermediate frequency counter System reset input Connecting crystal resonator for system clock oscillation Input Input -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Input Input Input Input P20 P21 P22 P33 P34 P36 P10 to P15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- After Reset Input Alternate Function P00, P01
Note Connect a capacitor of about 1000pF between the VDDPLL pin and GNDPLL pin.
Data Sheet U12628EJ3V0DS00
9
PD178002, 178003
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin Input/Output Circuits
Pin Name P00/INTP0 P01/INTP1, P02 to P06 P10/ANI0 to P12/ANI2 P13 to P15 P20/SI1 P21/SO1 P22/SCK1 P23 P24 P25 to P27 P30 to P32 P33/TI1, P34/TI2 P35 P36/BEEP P37 P40 to P47 P50 to P57 P60 to P63 P64 to P67 P120 to P125 P132 to P134 EO0, EO1 VCOL, VCOH AMIFC, FMIFC IC -- -- Connect directly to GND or GNDPORT. 19 DTS-EO1 DTS-AMP Input Output Set to low-level output by software and leave open. Leave open. Set to pin disabled status by software and leave open. 5-G 5 13-G 5 I/O Circuit Type 2 8 11-A 5 8 5 8 5 8 10 5 8 5 I/O Input I/O Recommended Connection of Unused Pins Connect to GND or GNDPORT. Set in general-purpose input port mode by software and independently connect to VDD, VDDPORT, GND, or GNDPORT via a resistor.
10
Data Sheet U12628EJ3V0DS00
PD178002, 178003
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2
Type 8
VDD IN Data P-ch IN/OUT Output disable Schmitt-triggered input with hysteresis characteristics N-ch
Type 5
Type 10
VDD Data P-ch IN/OUT Output disable N-ch Open drain Output disable Data
VDD P-ch IN/OUT N-ch
Input enable
Type 5-G
Type 11-A
VDD Data P-ch IN/OUT Output disable N-ch
VDD Data P-ch IN/OUT Output disable Comparator + _ N-ch VREF (Threshold voltage) Input enable N-ch P-ch
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports, and should be read as VDDPORT and GNDPORT, respectively.
Data Sheet U12628EJ3V0DS00
11
PD178002, 178003
Figure 3-1. Pin Input/Output Circuits (2/2)
Type 13-G
Type DTS-EO1
Data Output disable N-ch
IN/OUT DW
VDDPLL P-ch OUT
5 V withstand voltage input buffer UP Input enable N-ch GNDPLL
Type 19
Type DTS-AMP
VDDPLL OUT N-ch IN
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports, and should be read as VDDPORT and GNDPORT, respectively.
12
Data Sheet U12628EJ3V0DS00
PD178002, 178003
4. MEMORY SPACE
Figure 4-1 shows the PD178002 and 178003 memory map. Figure 4-1. Memory Map
FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH Data memory space FD00H FCFFH
General-purpose registers 32 x 8 bits
Internal high-speed RAM 512 x 8 bits
nnnnH Program area 1000H 0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH
Reserved
nnnnH + 1 nnnnH Program memory space 0000H 0040H 003FH
CALLT table area
Internal ROM Note
Vectored table area 0000H
Note The internal ROM capacity depends on the product (see the following table).
Part Number
Last Address of Internal ROM nnnnH 3FFFH 5FFFH
PD178002 PD178003
Data Sheet U12628EJ3V0DS00
13
PD178002, 178003
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports The following four types of I/O ports are available. * CMOS input (P00): * CMOS input/output (P01 to P06, port 1 to port 5, P64 to P67, port 12): * N-ch open-drain input/output (P60 to P63): * N-ch open-drain output (Port 13): Total: Table 5-1. Port Functions
Name Port 0 Pin Name P00 P01 to P06 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P10 to P15 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P63 P64 to P67 Port 12 Port 13 Input only Input/output port. Input/output can be specified in 1-bit units. Input/output port. Input/output can be specified in 1-bit units. Input/output port. Input/output can be specified in 1-bit units. Input/output port. Input/output can be specified in 1-bit units. Input/output port. Input/output can be specified in 8-bit units. The test flag (KRIF) is set to 1 by falling edge detection. Input/output port. Input/output can be specified in 1-bit units. N-ch open-drain input/output port. Input/output can be specified in 1-bit units. LEDs can be driven directly. Input/output port. Input/output can be specified in 1-bit units. Function
1 54 4 3 62
P120 to P125 Input/output port. Input/output can be specified in 1-bit units. P132 to P134 N-ch open-drain output port.
14
Data Sheet U12628EJ3V0DS00
PD178002, 178003
5.2 Clock Generator The instruction execution time can be changed as follows. 0.44 s/0.88 s/1.78 s/3.56 s/7.11 s/14.22 s (4.5 MHz crystal resonator for system clock.) Figure 5-1. Clock Generator Block Diagram
Prescaler X1 X2
Clock to the PLL frequency synthesizer, basic timer, and buzzer output control circuit.
System clock oscillator
fX Selector
Frequency divider
fXX
Prescaler fXX fXX fXX 2 22 23 fXX 24 Selector Standby control circuit
Clock to peripheral hardware other than the above.
STOP
fX 2
Wait control circuit
CPU clock (fCPU)
To INTP0 sampling clock
5.3 Timer Three timer channels are incorporated. * Basic timer: * 8-bit timer/event counter: 1 channel 2 channels Figure 5-2. Basic Timer Block Diagram
4.5 MHz
Frequency divider
INTTMC
Data Sheet U12628EJ3V0DS00
15
PD178002, 178003
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter
Internal bus INTTM1 8-bit compare register (CR10)
8-bit compare register (CR20) Selector Match INTTM2
Match fxx/2 to fxx/2 9 fx/2 11 TI1/P33 Selector 8-bit timer counter 1 (TM1) Selector Clear 8-bit timer counter 2 (TM2) Clear Selector Selector
fxx/2 to fxx/2 9 fx/2 11 TI2/P34
Internal bus
16
Data Sheet U12628EJ3V0DS00
PD178002, 178003
5.4 Buzzer Output Control Circuit Clocks with the following frequencies can be output as buzzer (BEEP) output. * 1.5 kHz/3 kHz/6 kHz (4.5 MHz crystal resonator for system clock) Figure 5-4. Block Diagram of Buzzer Output Control Circuit
3 kHz 6 kHz
Selector
1.5 kHz
BEEP/P36
3
TCL27 TCL26 TCL25 Timer clock select register 2 (TCL2)
P36 output latch
PM36 Port mode register 3 (PM3)
Internal bus
Data Sheet U12628EJ3V0DS00
17
PD178002, 178003
5.5 A/D Converter An A/D converter consisting of three 8-bit resolution channels is incorporated. The following two A/D conversion operation start-up methods are available. * Hardware start * Software start Figure 5-5. A/D Converter Block Diagram
Resistor string ANI0/P10 ANI1/P11 ANI2/P12 Selector Tap selector Sample & hold circuit Voltage comparator VDD
Successive approximation register (SAR)
GND
Control circuit
INTAD
A/D conversion result register (ADCR)
Internal bus
18
Data Sheet U12628EJ3V0DS00
PD178002, 178003
5.6 Serial Interfaces One clocked serial interface channel is incorporated. Serial interface channel 1 operates in the 3-wire serial I/O mode where MSB/LSB first can be switched. Figure 5-6. Block Diagram of Serial Interface Channel 1
Internal bus
SI1/P20
Serial I/O shift register 1 (SIO1)
SO1/P21
SCK1/P22
Serial clock counter
Interrupt request signal generator
INTCSI1
fXX/2 to fXX/2 8 Serial clock control circuit Selector
Data Sheet U12628EJ3V0DS00
19
PD178002, 178003
5.7 PLL Frequency Synthesizer Figure 5-7. Block Diagram of PLL Frequency Synthesizer
Internal bus PLL mode select register (PLLMD) PLL data transfer register (PLLNS)
PLL PLL MD1 MD0 2
PLL data register (PLLRL, PLLRH, PLLR0) 2 fN
PLL NS0
VCOH Mixer VCOL Input select block Programmable divider
fr
Phase comparator ( -DET)
EO1 Charge pump EO0
Voltage control generator
Note
4.5 MHz
Reference frequency generator
Unlock FF
4
Note
Low pass filter
PLL PLL PLL PLL PLL RF3 RF2 RF1 RF0 UL0 PLL unlock PLL reference FF judge mode register register (PLLRF) (PLLUL) Internal bus
Note External circuit
20
Data Sheet U12628EJ3V0DS00
PD178002, 178003
5.8 Frequency Counter Figure 5-8. Frequency Counter Block Diagram
2
Gate time control block
FMIFC Input select block AMIFC
Start/stop control block
IF counter register (IFC) block
2
IFC IFC IFC IFC MD1 MD0 CK1 CK0 IF counter mode select register (IFCMD) IF counter gate judge register (IFCJG)
IFC JG0
IFC IFC ST RES IF counter control register (IFCR)
Internal bus
Data Sheet U12628EJ3V0DS00
21
PD178002, 178003
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 Interrupt Functions A total of 8 interrupt sources are provided, divided into the following two types. * Maskable: 7 * Software: 1 Table 6-1. Interrupt Source List
Note 1
Interrupt Type Maskable
Interrupt Source Name INTP0 INTP1 INTCSI1 INTTMC INTTM1 INTTM2 INTAD BRK End of serial interface channel 1 transfer Generation of matching signal of basic timer Generation of matching signal of 8-bit timer/event counter 1 Generation of matching signal of 8-bit timer/event counter 2 End of conversion by A/D converter Execution of BRK instruction Trigger Pin input edge detection
Default Priority 0 1 2 3 4 5 6
Internal/ External External
Vector Table Address 0006H 0008H
Basic Configuration TypeNote 2 (A) (B) (C)
Internal
0016H 0018H 001CH 001EH 0020H
Software
--
--
003EH
(D)
Notes 1. The default priority is a priority order when several maskable interrupts are generated at the same time. 0 is the highest order and 6 is the lowest order. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 6-1.
22
Data Sheet U12628EJ3V0DS00
PD178002, 178003
Figure 6-1. Basic Configuration of Interrupt Function (1/2) (A) External maskable interrupt (INTP0)
Internal bus
Sampling clock select register (SCS)
External interrupt mode register (INTM0)
MK
IE
PR
ISP
Interrupt request
Sampling clock
Edge detection circuit
IF
Priority control circuit
Vector table address generator Standby release signal
(B) External maskable interrupt (INTP1)
Internal bus
External interrupt mode register (INTM0)
MK
IE
PR
ISP
Interrupt request
Edge detection circuit
IF
Priority control circuit
Vector table address generator Standby release signal
Data Sheet U12628EJ3V0DS00
23
PD178002, 178003
Figure 6-1. Basic Configuration of Interrupt Function (2/2) (C) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority control circuit
Vector table address generator Standby release signal
(D) Software interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generator
IF: IE:
Interrupt request flag Interrupt enable flag
ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag
24
Data Sheet U12628EJ3V0DS00
PD178002, 178003
6.2 Test Function Table 6-2 shows a test function available. Table 6-2. Test Input Source List
Test Input Source Name INTPT4 Trigger Port 4 falling edge detection Internal/External External
Figure 6-2. Basic Configuration of Test Function
Internal bus
MK
Test input
IF
Standby release signal
IF:
Test input flag
MK: Test mask flag
Data Sheet U12628EJ3V0DS00
25
PD178002, 178003
7. STANDBY FUNCTION
The following two standby functions are available for further reduction of system current consumption. * HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. * STOP mode: In this mode, oscillation of the system clock is stopped. All the operations performed on the system clock are suspended, resulting in extremely small power consumption. Figure 7-1. Standby Function
System clock operation STOP instruction Interrupt request HALT mode (Clock supply to CPU halted, oscillation maintained) HALT instruction
Interrupt request
STOP mode (System clock oscillation stopped)
8. RESET FUNCTION
The following two reset methods are available. * External reset by RESET signal input * Internal reset by Power On Clear (POC).
26
Data Sheet U12628EJ3V0DS00
PD178002, 178003
9. INSTRUCTION SET
(1) 8-bit instructions MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand 1st Operand A #byte A r
[HL + byte]
Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B] [HL + C]
$addr16
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
INC DEC
B,C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV
DBNZ
DBNZ
INC DEC
!addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] X C MOV
MOV MOV PUSH POP ROR4 ROL4
MOV MOV
MULU DIVUW
Note Except r = A
Data Sheet U12628EJ3V0DS00
27
PD178002, 178003
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand 1st Operand AX #word ADDW SUBW CMPW rp sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW Note MOVW MOVW MOVW MOVW AX rp Note MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None
INCW, DECW PUSH, POP
Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand 1st Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY MOV1 $addr16 BT BF BTCLR BT BF BTCLR saddr.bit MOV1 BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 None SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
(4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand 1st Operand Basic instruction Compound instruction BR AX !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC BZ, BNZ BT, BF BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
28
Data Sheet U12628EJ3V0DS00
PD178002, 178003
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Input voltage Output voltage Output withstand voltage Analog input voltage Output current, high Symbol VDD VI VO VBDS VAN IOH P132 to P134 P10 to P12 Per pin Total for P01 to P06, P30 to P37, P56, P57, P60 to P67, P120 to P125 Total for P10 to P15, P20 to P27, P40 to P47, P50 to P55, P132 to P134 Output current, low IOLNote Per pin Peak value rms value Operating ambient temperature Storage temperature TA Tstg 15 7.5 -40 to +85 -65 to +150 mA mA C C N-ch open drain Analog input pin Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -10 -15 -15 Unit V V V V V mA mA mA
Note The rms value should be calculated as follows: [rms value] = [Peak value] x Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Recommended Supply Voltage Ranges (TA = -40 to +85C)
Parameter Supply voltage Symbol VDD1 VDD2 VDD3 Conditions During CPU operation and PLL operation. While the CPU is operating and the PLL is stopped. Cycle time: TCY 0.89 s While the CPU is operating and the PLL is stopped. Cycle time: TCY = 0.44 s MIN. 4.5 3.5 4.5 TYP. MAX. 5.5 5.5 5.5 Unit V V V
Remark TCY: Cycle time (minimum instruction execution time)
Data Sheet U12628EJ3V0DS00
29
PD178002, 178003
DC Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter Input voltage, high Symbol VIH1 P10 P30 P40 P64 to to to to P15, P32, P47, P67, Conditions P21, P23, P35 to P37, P50 to P57, P120 to P125 MIN. 0.7VDD TYP. MAX. VDD
(1/3)
Unit V
VIH2
P00 to P06, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 (N-ch open drain) P10 P30 P40 P64 to to to to P15, P32, P47, P67, P21, P23, P35 to P37, P50 to P57, P120 to P125
0.85VDD
VDD
V
VIH3 Input voltage, low VIL1
0.7VDD 0
VDD 0.3VDD
V V
VIL2
P00 to P06, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 (N-ch open drain) 4.5 V VDD 5.5 V, IOH = -1 mA 3.5 V VDD < 4.5 V, IOH = -100 A
0
0.15VDD
V
VIL3 Output voltage, high VOH1
0 VDD - 1.0 VDD - 0.5 0.4
0.2VDD
V V V
Output voltage, low
VOL1
P50 to P57, P60 to P63 P01 to P06, P10 to P15, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P120 to P125, P132 to P134
VDD = 4.5 to 5.5 V, IOH = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA
2.0 0.4
V V
VOL2
SB0, SB1, SCK0
VDD = 4.5 to 5.5 V, N-ch open drain, pulled-up (R = 1 K)
0.2VDD
V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
30
Data Sheet U12628EJ3V0DS00
PD178002, 178003
DC Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 Conditions P00 to P06, P10 to P15, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P120 to P125, RESET P60 to P63 P00 to P06, P10 to P15, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P120 to P125, RESET P60 to P63 P132 to P134 P132 to P134 EO0, EO1 VOUT = VDD VOUT = 0 V VOUT = VDD, VOUT = 0 V VIN = VDD MIN. TYP. MAX. 3
(2/3)
Unit
A
ILIH2 Input leakage current, low ILIL1
VIN = VDD VIN = 0 V
80 -3
A A
ILIL2 Output leakage current, high Output leakage current, low Output off leakage current ILOL ILOF ILOH
-3Note 3 -3 1
A A A A
Note When an input instruction is executed to P60 to P63, a low-level input leakage current of -200 A (MAX.) flows only for one clock. At times other than this 1-clock interval, a -3 A (MAX.) current flows. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Reference Characteristics (TA = 25C, VDD = 5 V)
Parameter Output current, high Symbol IOH1 EO0 EO1 Output current, low IOL1 EO0 EO1 VOUT = 1 V 3.5 Conditions VOUT = VDD - 1 V -1.8 6 MIN. TYP. -4 MAX.
(1/2)
Unit mA mA mA mA
Data Sheet U12628EJ3V0DS00
31
PD178002, 178003
DC Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter Power supply currentNote 1 Symbol IDD1 IDD2 IDD3 Conditions While the CPU is operating and the PLL is stopped fX = 4.5 MHz operation TCY = 0.89 sNote 2 TCY = 0.44 sNote 3 VDD = 4.5 to 5.5 V TCY = 0.89 sNote 2 MIN. TYP. 2.5 4.0 0.7 MAX. 15 27 1.5
(3/3)
Unit mA mA mA
IDD4
While the CPU is operating and the PLL is stopped HALT Mode Pin X1 sine wave input VIN = VDD. fX = 4.5 MHz operation
TCY = 0.44 sNote 3 VDD = 4.5 to 5.5 V 4.5 3.5 2.6
1.0
2.0
mA
Data retention VDDR1 power supply voltage VDDR2 VDDR3 Data retention power supply current IDDR1 IDDR2
When the crystal oscillation TCY = 0.44 s is operating TCY = 0.89 s When the crystal oscillation is stopped When power off by power on clear is detected When the crystal oscillation TA = 25C, VDD = 5 V is stopped
5.5 5.5 5.5 2 2 4 30
V V V
A A
Notes 1. The current flowing to the ports is not included. 2. When the processor clock control register (PCC) is set to 00H, and the oscillation mode select register (OSMS) is set to 00H. 3. When PCC is set to 00H and OSMS is set to 01H. Remarks 1. TCY: Cycle time (minimum instruction execution time) 2. fX: System clock oscillation frequency. Reference Characteristics (TA = 25C, VDD = 5 V)
Parameter Power supply current Symbol IDD5 During CPU operation and PLL operation. VCOH pin sine wave input fIN = 130 MHz, VIN = 0.15 Vp-p Conditions TCY = 0.44 sNote MIN. TYP. 7 MAX.
(2/2)
Unit mA
Note When the processor clock control register (PCC) is set to 00H, and the oscillation mode select register (OSMS) is set to 01H. Remark TCY: Cycle time (minimum instruction execution time)
32
Data Sheet U12628EJ3V0DS00
PD178002, 178003
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter Cycle time (Minimum instruction execution time) TI1, TI2 input frequency TI1, TI2 input high-/ low-level width Interrupt input high-/ low-level width RESET low level width fTI Symbol TCY fXNote 2, Conditions fXX = fX/2Note 1, fX = 4.5 MHz operation fXX = fX = 4.5 MHz operation 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V tTIH, tTIL tINTH, tINTL tRSL 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V INTP0 INTP1 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 0.89 0.44 0.89 0 0 111 1.8 8/fsamNote 3 10 10 TYP. MAX. 14.22 7.11 7.11 4.5 275 Unit
s s s
MHz kHz ns
s s s s
Notes 1. When the oscillation mode select register (OSMS) is set to 00H. 2. When OSMS is set to 01H. 3. Selection of fsam = fXX/2N, fXX/32, fXX/64, fXX/128 is possible with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS) (when N = 0 to 4). Remarks 1. fXX: System clock frequency (fX or fX/2) 2. fX: System clock oscillation frequency TCY vs. VDD (At fXX = fX/2 system clock operation) TCY vs. VDD (At fXX = fX system clock operation)
60
60
10
Cycle time TCY [ s] Cycle time TCY [ s]
10 Guaranteed operation range
2.0 1.0 0.5 0.4
2.0 1.0 0.5 0.4
Guaranteed operation range
0 1 2 3 4 5 6 Supply voltage VDD [V]
0 1 2 3 4 5 6 Supply voltage VDD [V]
Data Sheet U12628EJ3V0DS00
33
PD178002, 178003
(2) Serial interface (TA = -40 to +85C, VDD = 3.5 to 5.5 V) (a) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter SCK1 cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK1 high-/low-level width tKH1, tKL1 SI1 setup time (to SCK1) tSIK1 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI1 hold time (from SCK1) tKSI1 C = 100 pFNote MIN. 800 1600 tKCY9/2 - 50 tKCY9/2 - 100 100 150 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SO1 output delay time from SCK1 tKSO1
Note C is the load capacitance of the SO1 output line. (ii) 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter SCK1 cycle time Symbol tKCY2 Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK1 high-/low-level width tKH2, tKL2 SI1 setup time (to SCK1) SI1 hold time (from SCK1) tSIK2 tKSI2 C = 100 pFNote 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1600 400 800 100 400 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SO1 output delay time from SCK1 tKSO2 SCK1 rise/fall time tR2, tF2
Note C is the load capacitance of the SO1 output line.
34
Data Sheet U12628EJ3V0DS00
PD178002, 178003
AC Timing Test Points (excluding X1 input)
0.8VDD 0.2VDD
Test points
0.8VDD 0.2VDD
TI Timing
1/fTI
tTIL
tTIH
TI1, TI2
Interrupt Input Timing
tINTL
tINTH
INTP0, INTP1
RESET Input Timing
tRSL
RESET
Data Sheet U12628EJ3V0DS00
35
PD178002, 178003
Serial Transfer Timing 3-wire serial I/O mode:
tKCY1, 2 tKL1, 2 tR2 SCK1 tSIK1, 2 tKSI1, 2 tKH1, 2 tF2
SI1 tKSO1, 2
Input data
SO1
Output data
36
Data Sheet U12628EJ3V0DS00
PD178002, 178003
A/D Converter Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Resolution Conversion overall error Conversion time Sampling time Analog input voltage tCONV tSAMP VIAN 22.2 15/fXX 0 VDD Symbol Conditions MIN. 8 TYP. 8 MAX. 8 3.0 44.4 Unit bit LSB
s s
V
Remarks 1. fXX: System clock frequency (fX/2) 2. fX: System clock oscillation frequency PLL Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Operating frequency Symbol fIN1 fIN2 fIN3 Conditions VCOL pin MF mode Sine wave input VIN = 0.1 Vp-p VCOL pin HF mode Sine wave input VIN = 0.2 Vp-p VCOH pin VHF mode Sine wave input VIN = 0.15 Vp-p MIN. 0.5 9 60 TYP. MAX. 3 55 160 Unit MHz MHz MHz
IFC Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Operating frequency Symbol fIN4 fIN5 fIN6 Conditions AMIFC pin AMIF count mode Sine wave input VIN = 0.1 Vp-pNote FMIFC pin FMIF count mode Sine wave input VIN = 0.1 Vp-pNote FMIFC pin AMIF count mode Sine wave input VIN = 0.1 Vp-pNote MIN. 0.4 10 0.4 TYP. MAX. 0.5 11 0.5 Unit MHz MHz MHz
Note The condition of a sine wave input of VIN = 0.1 Vp-p is the standard value of this device during standalone operation, so in consideration of the effect of noise, operation of an input amplitude condition of VIN = 0.15 Vp-p is recommended.
Data Sheet U12628EJ3V0DS00
37
PD178002, 178003
11. PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S CD Q R
80 1
21 20
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. S80GC-65-3B9-6
38
Data Sheet U12628EJ3V0DS00
PD178002, 178003
12. RECOMMENDED SOLDERING CONDITIONS
The PD178002 and 178003 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 12-1. Surface Mounting Type Soldering Conditions
PD178002GC-xxx-3B9: PD178003GC-xxx-3B9:
Soldering Method Infrared reflow VPS Wave soldering Partial heating
80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch)
Soldering Conditions Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1 --
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: once, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U12628EJ3V0DS00
39
PD178002, 178003
APPENDIX A. DIFFERENCES AMONG PD178003 AND PD178018A SUBSERIES
Product Name PD178003 Subseries Items ROM RAM High-speed RAM Buffer RAM Expanded RAM Timer
PD178018A Subseries PD178006A
48 Kbytes (Mask ROM) 1024 byte 32 bytes 2048 bytes 5 channels * Basic timer: * 8-bit timer/event counter: * 8-bit timer: * Watchdog timer: 1 2 1 1 channel channels channel channel
PD178003
24 Kbytes (Mask ROM) 512 bytes Not provided Not provided 3 channels * Basic timer: 1 channel * 8-bit timer/event counter: 2 channels 1 channel * 3-wire mode: 1 channel
PD178018A
60 Kbytes (Mask ROM)
PD178P018A
60 Kbytes (One-time PROM)
Serial interface
2 channels * 3-wire/SBI/2-wire/I2C bus mode selectable: 1 channel * 3-wire serial I/O mode (automatic data transmit/receive function for up to 32 bytes provided on chip): 1 channel 6 channels Provided Buffer type (high impedance function supported)
A/D converter D/A converter (PWM output) EO1 pin output circuit
3 channels Not provided
Buffer type (high impedance function not supported)
40
Data Sheet U12628EJ3V0DS00
PD178002, 178003
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD178003 Subseries. Also refer to (5) Cautions on using development tools. (1) Language processing software
RA78K0 CC78K0 DF178018 CC78K0-L Assembler package common to 78K/0 Series C compiler package common to 78K/0 Series Device file for PD178003 and PD178018A Subseries C compiler library source file common to 78K/0 Series
(2) PROM writing tools
PG-1500 PG-178P018GC PA-178P018KK-T PG-1500 controller PG-1500 control program PROM programmer Programmer adapters connected to PG-1500
(3) Debugging tools * When IE-78K0-NS in-circuit emulator is used
IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PANote IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF IE-178018-NS-EM1 NP-80GC EV-9200GC-80 ID78K0-NS SM78K0 DF178018 In-circuit emulator common to 78K/0 Series Power supply unit for IE-78K0-NS Performance board for enhancing and extending the function of the IE-78K0-NS Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) PC card and interface cable when using notebook PC of PC-9800 series as host machine (PCMCIA socket supported) Interface adapter when using IBM PC/ATTM-compatible as host machine (ISA bus supported) Interface adapter required when using a PCI bus incorporated computer as host machine Emulation board to emulate PD178003, 178018A Subseries Emulation probe for 80-pin plastic QFP (GC-3B9 type) Socket to be mounted on a target system board made for 80-pin plastic QFP (GC-3B9 type) Integrated debugger for IE-78K0-NS System simulator common to 78K/0 Series Device file for PD178003 and PD178018A Subseries
Note Under development
Data Sheet U12628EJ3V0DS00
41
PD178002, 178003
* When IE-78001-R-A in-circuit emulator is used
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF IE-78000-R-SV3 IE-178018-NS-EM1 IE-78K0-R-EX1 IE-178018-R-EM EP-78230GC-R EV-9200GC-80 EV-9900 ID78K0 SM78K0 DF178018 In-circuit emulator common to 78K/0 Series Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) Interface adapter when using IBM PC/AT-compatible as host machine (ISA bus supported) Adapter required when using a PCI bus incorporated computer as host machine Interface adapter and cable when using EWS as host machine Emulation board to emulate PD178003, 178018A Subseries Emulation probe conversion board required when using IE-178018-NS-EM1 on IE-78001-R-A Emulation board to emulate PD178003, 178018A Subseries Emulation probe for 80-pin plastic QFP (GC-3B9 type) Socket to be mounted on a target system board made for 80-pin plastic QFP (GC-3B9 type) Tool used for removing PD178P018AKK-T from EV-9200GC-80 Integrated debugger for IE-78001-R-A System simulator common to 78K/0 Series Device file for PD178003 and PD178018A Subseries
(4) Real-time OS
RX78K/0 MX78K0 Real-time OS for 78K/0 Series OS for 78K/0 Series
42
Data Sheet U12628EJ3V0DS00
PD178002, 178003
(5) Cautions on using development tools * The ID-78K0-NS, ID78K0, and SM78K0 are used in combination with the DF178018. * The RX78K/0 is used in combination with the RA78K0 and the DF178018. * The NP-80GC is a product made by Naito Densei Machida Mfg. Co., Ltd (TEL +81-44-822-3813). Contact an NEC distributor regarding the purchase of this product. * For third party development tools, see the Single-chip Microcontroller Development Tools Selection Guide (U11069E). * The host machine and OS suitable for each software are as follows:
Host Machine [OS] Software RA78K0 CC78K0 PG-1500 controller ID78K0-NS ID78K0 SM78K0 RX78K/0 MX78K0 PC PC-9800 series [WindowsTM] IBM PC/AT-compatible [Japanese/English Windows] Note Note Note Note Note EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM and SolarisTM] NEWS (RISC)TM [NEWS-OSTM] -- -- --
Note DOS-based software
Data Sheet U12628EJ3V0DS00
43
PD178002, 178003
APPENDIX C. RELATED DOCUMENTS
Documents Related to Devices
Document Name Document No. English Japanese U12642J U13033J U12326J U10904J U10903J U10121J
PD178P018A Data Sheet PD178003 Subseries User's Manual
78K/0 Series User's Manual--Instruction 78K/0 Series Instruction Set 78K/0 Series Instruction Table 78K/0 Series Application Note Basics (II)
U12642E U13033E U12326E -- -- U10121E
Documents Related to Development Tools (User's Manuals)
Document Name Document No. English RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller PC-9800 series (MS-DOS) Based PG-1500 Controller IBM PC series (PC DOS) Based IE-78K0-NS IE-78001-R-A IE-78K0-R-EX1 IE-178018-NS-EM1 IE-178018-R-EM EP-78230 SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference Reference Guide EEU-1402 U11517E U11518E U11940E EEU-1291 U10540E -- To be prepared To be prepared U14012E U10668E EEU-1515 U10181E U10092E U12323J U11517J U11518J U11940J EEU-704 EEU-5008 U13731J To be prepared To be prepared U14012J U10668J EEU-985 U10181J U10092J U11802E U11801E U11789E Japanese U11802J U11801J U11789J
ID78K0-NS Integrated Debugger Windows Based ID78K0 Integrated Debugger EWS Based ID78K0 Integrated Debugger PC Based ID78K0 Integrated Debugger Windows Based
U12900E -- U11539E U11649E
U12900J U11151J U11539J U11649J
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
44
Data Sheet U12628EJ3V0DS00
PD178002, 178003
Documents Related to Embedded Software (User's Manuals)
Document Name Document No. English 78K/0 Series Real-Time OS Fundamentals Installation 78K/0 Series OS MX78K0 Fundamental U11537E U11536E U12257E Japanese U11537J U11536J U12257J
Other Related Documents
Document Name Document No. English SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System X13769X C10535E C11531E C10983E C10535J C11531J C10983J C11892J U11416J Japanese
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Guide to Microcomputer-Related Products by Third Party --
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U12628EJ3V0DS00
45
PD178002, 178003
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
46
Data Sheet U12628EJ3V0DS00
PD178002, 178003
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U12628EJ3V0DS00
47
PD178002, 178003
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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